This implementation uses a Xilinx complex programmable logic device (CPLD) to count the pulses from the encoder and determine the direction indicated by those pulses (see the figure). The design ...

Sydney, March 28 2011 --Today Ocean Logic announces ... 264 CFS Encoder IP core is immediately available as VHDL or Verilog source or FPGA netlist. The H.264 limited decoder will be available in Q2.

FTMCP100 is a video and image compression / decompresion IP core that supports the MPEG-4 (ISO/IEC 14496-2) and JPEG (ISO/IEC 10918-1); UMC 0.13um HS/FSG Logic Process View Video Encoder/Decoder -- ...

The company’s expanded platform provides ST 2110 support for encoders, decoders ... Digital will be showing several units of its Sapphire converter family that deliver high-quality design ...