When system tasks appear in the generated Verilog, this code in Verilog.hs omits the parenthesis when there are no arguments: -- no parens when calling a task if it has no arguments pPrint d p ...

The intent is to make an accessible library of common functions for writing Verilog code. Filters, signal transforms, I/O modules, and more are all fair game. You can either drop these in your project ...